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general description the max15012/max15013 high-frequency, 175v half- bridge, n-channel mosfet drivers drive high- and low- side mosfets in high-voltage applications. these drivers are independently controlled and their 35ns typ- ical propagation delay, from input to output, are matched to within 2ns (typ). the high-voltage operation with very low and matched propagation delay between drivers, and high source/sink current capabilities make these devices suitable for the high-power, high-fre- quency telecom power converters. a reliable on-chip bootstrap diode connected between v dd and bst eliminates the need for an external discrete diode. the max15012a/c and max15013a/c offer both nonin- verting drivers (see the selector guide ). the max15012b/d and max15013b/d offer a noninverting high-side driver and an inverting low-side driver. the max15012a/b/c/d feature cmos (v dd /2) logic inputs. the max15013a/b/c/d feature ttl logic inputs. the drivers are available in the industry-standard 8-pin so footprint and pin configuration and a thermally enhanced 8-pin so package. all devices operate over the -40? to +125? automotive temperature range. applications telecom half-bridge power supplies two-switch forward converters full-bridge converters active-clamp forward converters power-supply modules motor control features ? hip2100/hip2101 pin compatible (max15012a/c and max15013a/c) ? up to 175v input operation ? 8v to 12.6v v dd input voltage range ? 2a peak source and sink current drive capability ? 35ns typical propagation delay ? guaranteed 8ns propagation delay matching between drivers ? up to 500khz switching frequency ? available in cmos (v dd /2) or ttl logic-level inputs with hysteresis ? up to 14v logic inputs independent of input voltage ? low 2.5pf input capacitance ? low 70 a supply current ? versions available with combination of noninverting and inverting drivers (max15012b/d and max15013b/d) ? available in industry-standard 8-pin so and thermally enhanced so packages max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers ________________________________________________________________ maxim integrated products 1 part temp range pin- package pkg code max15012 aasa+ -40? to +125? 8 so s8-5 max15012basa+ -40? to +125? 8 so s8-5 MAX15012CASA+* -40? to +125? 8 so-ep** s8e+14 max15012dasa+* -40? to +125? 8 so-ep** s8e+14 ordering information part high-side driver low-side driver logic levels pin compatible max15012aasa+ noninverting noninverting cmos (v dd /2) hip 2100ib max15012basa+ noninverting inverting cmos (v dd /2) MAX15012CASA+ noninverting noninverting cmos (v dd /2) hip 2100ib max15012dasa+ noninverting inverting cmos (v dd /2) max15013aasa+ noninverting noninverting ttl hip 2101ib max15013basa+ noninverting inverting ttl max15013casa+ noninverting noninverting ttl hip 2101ib max15013dasa+ noninverting inverting ttl selector guide 19-0530; rev 1; 12/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information continued at end of data sheet. + denotes lead-free package. * future product?ontact factory for availability. ** ep = exposed pad. pin configurations and typical operating circuit appear at the end of data sheet.
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = v bst = +8v to +12.6v, v hs = gnd = 0v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at v dd = v bst = +12v and t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd, unless otherwise noted.) v dd , in_h, in_l......................................................-0.3v to +14v dl ...............................................................-0.3v to (v dd + 0.3v) hs............................................................................-5v to +180v dh to hs.....................................................-0.3v to (v dd + 0.3v) bst to hs ...............................................................-0.3v to +14v dv/dt at hs ........................................................................50v/ns continuous power dissipation (t a = +70?) 8-pin so (derate 5.9mw/? above +70?)...............470.6mw 8-pin so-ep (derate 19.2mw/? above +70?) .....1538.5mw junction-to-case thermal resistance ( jc )(note 1) 8-pin so .......................................................................40?/w 8-pin so-ep....................................................................6?/w junction-to-ambient thermal resistance ( ja )(note 1) 8-pin so .....................................................................170?/w 8-pin so-ep..................................................................52?/w maximum junction temperature .....................................+150? operating temperature range .........................-40? to +125? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units power supplies operating supply voltage v dd (notes 3 and 4) 8.0 12.6 v v dd quiescent supply current (no switching) i dd in_h = in_l = gnd (for a/c versions), in_h = gnd, in_l = v dd (for b/d versions) 70 140 ? v dd operating supply current i ddo f sw = 500khz, v dd = +12v 3 ma bst quiescent supply current i bst in_h = in_l = gnd (for a/c versions), in_h = gnd, in_l = v dd (for b/d versions) 15 40 ? bst operating supply current i bsto f sw = 500khz, v dd = v bst = +12v 3 ma uvlo (v dd to gnd) uvlo vdd v dd rising 6.5 7.3 8.0 v uvlo (bst to hs) uvlo bst bst rising 6.0 6.9 7.8 v uvlo hysteresis 0.5 v logic input max15012_, cmos (v dd /2) version 0.67 x v dd 0.55 x v dd input-logic high v ih_ max15013_, ttl version 2 1.65 v max15012_, cmos (v dd /2) version 0.4 x v dd 0.33 x v dd input-logic low v il_ max15013_, ttl version 1.4 0.8 v max15012_, cmos (v dd /2) version 1.6 logic-input hysteresis v hys max15013_, ttl version 0.25 v * per jedec 51 standard multilayer board. note 1: package thermal resistances were obtained using the method described in jedec specification je5d51-7, using a four- layer board. for detailed information on package thermal considerations, see www.maxim-ic.com/thermal-tutorial .
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = v bst = +8v to +12.6v, v hs = gnd = 0v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at v dd = v bst = +12v and t a = +25?.) (note 2) parameter symbol conditions min typ max units v in_l = v dd for max15012b/max15012d/ max15013b/max15013d v in_h = 0v logic-input current i _in v in_l = 0v for max15012a/max15012c/ max15013a/max15013c -1 +0.001 +1 ? in_h to gnd in_l to v dd for max15012b/max15012d/ max15013b/max15013d input resistance r in in_l to gnd for max15012a/max15012c/ max15013a/max15013c 1m input capacitance c in 2.5 pf high-side gate driver hs maximum voltage v hs_max v dd 10.5v (note 4) 175 v bst maximum voltage v bst_max v dd 10.5v (note 4) 189 v t a = +25? 2.5 3.3 driver output resistance (sourcing) r on_hp v dd = 12v, i dh = 100ma (sourcing) t a = +125? 3.5 4.6 t a = +25? 2.1 2.8 driver output resistance (sinking) r on_hn v dd = 12v, i dh = 100ma (sinking) t a = +125? 3.2 4.2 dh reverse current (latchup protection) (note 5) 400 ma power-off pulldown clamp voltage v bst = 0v or floating, i dh = 1ma (sinking) 0.94 1.16 v peak output current (sourcing) c l = 10nf, v dh = 0v 2 a peak output current (sinking) i dh_peak c l = 10nf, v dh = 12v 2 a low-side gate driver t a = +25? 2.5 3.3 driver output resistance (sourcing) r on_lp v dd = 12v, i dl = 100ma (sourcing) t a = +125? 3.5 4.6 t a = +25? 2.1 2.8 driver output resistance (sinking) r on_ln v dd = 12v, i dl = 100ma (sinking) t a = +125? 3.2 4.2 reverse current at dl (latchup protection) (note 5) 400 ma power-off pulldown clamp voltage v dd = 0v or floating, i dl = 1ma (sinking) 0.95 1.16 v peak output current (sourcing) i pk_lp c l = 10nf, v dl = 0v 2 a peak output current (sinking) i pk_ln c l = 10nf, v dl = 12v 2 a internal bootstrap diode forward voltage drop v f i bst = 100ma 0.91 1.11 v turn-on and turn-off time t r i bst = 100ma 40 ns
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers 4 _______________________________________________________________________________________ note 2: all devices are 100% tested at t a = +125?. limits over temperature are guaranteed by design. note 3: ensure that the v dd -to-gnd or bst-to-hs transient voltage does not exceed 13.2v. note 4: maximum operating supply voltage (v dd ) reduces linearly from 12.6v to 10.5v with its maximum voltage (v hs_max ) increasing from 125v to 175v. see the typical operating characteristics and applications information sections. note 5: guaranteed by design, not production tested. note 6: see the minimum input pulse width section. electrical characteristics (continued) (v dd = v bst = +8v to +12.6v, v hs = gnd = 0v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at v dd = v bst = +12v and t a = +25?.) (note 2) parameter symbol conditions min typ max units switching characteristics for high- and low-side drivers (v dd = v bst = +12v) c l = 1000pf 7 c l = 5000pf 33 rise time t r c l = 10,000pf 65 ns c l = 1000pf 7 c l = 5000pf 33 fall time t f c l = 10,000pf 65 ns cmos 30 55 turn-on propagation delay time t d_on figure 1, c l = 1000pf (note 5) ttl 35 63 ns cmos 30 55 turn-off propagation delay time t d_off figure 1, c l = 1000pf (note 5) ttl 35 63 ns delay matching between driver- low and driver-high t match c l = 1000pf, figure 1 (note 5) 2 8 ns internal nonoverlap 1ns v dd = v bst = 12v 135 minimum pulse width input logic (note 6) t pw-min v dd = v bst = 8v 170 ns
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers _______________________________________________________________________________________ 5 undervoltage lockout (v dd and v bst rising) vs. temperature max15012/13 toc01 temperature ( c) uvlo (v) 110 95 65 80 -10 5 20 35 50 -25 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 7.5 6.5 -40 125 uvlo vdd uvlo bst v dd and bst undervoltage lockout hysteresis vs. temperature max15012/13 toc02 temperature ( c) uvlo hysteresis (v) 110 95 65 80 -10 5 20 35 50 -25 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -40 125 uvlo bst hysteresis uvlo vdd hysteresis i dd vs. v dd max15012/13 toc03 4ms/div v dd 2v/div i dd 50 a/div 0 a 0v in_h = gnd in_l = v dd i ddo + i bsto vs. v dd (f sw = 250khz) max15012/13 toc04 v dd (v) i ddo + i bsto (ma) 12 10 11 3456789 12 1.0 0.8 0.6 0.4 0.2 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 0 013 0 60 40 20 80 100 120 140 160 180 200 0.5 0.7 0.6 0.8 0.9 1.0 1.1 internal bst diode (i-v) characteristics max15012/13 toc05 v dd - v bst (v) i diode (ma) t a = +125 c t a = +25 c t a = 0 c t a = -40 c 0 60 40 20 80 100 120 140 160 04 26 8 10 12 v dd quiescent current vs. v dd (no switching) max15012/13 toc06 v dd (v) i dd ( a) t a = -40 c t a = +25 c v dd = v bst v hs = gnd in_h = gnd in_l = v dd t a = +125 c 0 6 3 9 12 15 18 21 04 26810 15 3 7 9 1112131415 bst quiescent current vs. bst voltage max15012/13 toc07 v bst (v) i bst ( a) v bst = v dd + 1v, no switching t a = +125 c t a = -40 c, t a = 0 c, t a = +25 c typical operating characteristics (typical values are at v dd = v bst = +12v and t a = +25?, unless otherwise specified.)
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers 6 _______________________________________________________________________________________ v dd and bst operating supply current vs. frequency max15012/13 toc08 frequency (khz) i ddo + i bsto (ma) 900 700 800 200 300 400 500 600 100 1 2 3 4 5 6 7 8 9 10 0 0 1000 c l = 0 dh or dl output low voltage vs. temperature max15012/13 toc09 temperature ( c) output low voltage (v) 110 95 65 80 -10 5 20 35 50 -25 0.12 0.14 0.16 0.18 0.20 0.24 0.28 0.32 0.34 0.22 0.26 0.30 0.10 -40 125 sinking 100ma dh or dl fall time vs. temperature (c load = 10nf) max15012/13 toc12 temperature ( c) t f (ns) 110 95 65 80 -10 5 20 35 50 -25 10 20 30 40 50 70 110 100 90 120 60 80 0 -40 125 v dd = v bst = 8v v dd = v bst = 12v dh or dl rise propagation delay vs. temperature max15012/13 toc13 temperature ( c) propagation delay (ns) 110 95 65 80 -10 5 20 35 50 -25 5 10 15 20 25 35 55 60 30 45 50 40 0 -40 125 dh dl peak dh and dl source/sink current max15012/13 toc10 1 s/div dh or dl 5v/div sink and source current 2a/div c l = 100nf dh or dl rise time vs. temperature (c l = 10nf) max15012/13 toc11 temperature ( c) t r (ns) 110 95 65 80 -10 5 20 35 50 -25 12 24 36 48 60 84 108 120 72 96 0 -40 125 v dd = v bst = 8v v dd = v bst = 12v typical operating characteristics (continued) (typical values are at v dd = v bst = +12v and t a = +25?, unless otherwise specified.)
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers _______________________________________________________________________________________ 7 dh or dl fall propagation delay vs. temperature max15012/13 toc14 temperature ( c) propagation delay (ns) 110 95 65 80 -10 5 20 35 50 -25 5 10 15 20 25 35 55 60 30 45 50 40 0 -40 125 dh dl v hs_max vs. v dd_max max15012/13 toc15 v dd_max (v) v hs_max (v) 10.5 175 125 0 8 12.6 delay matching (dh/dl rising) max15012/13 toc16 10ns/div input 5v/div dh/dl 5v/div c l = 0 delay matching (dh/dl falling) max15012/13 toc17 10ns/div c l = 0 input 5v/div dh/dl 5v/div dh/dl response to v dd glitch max15012/13 toc18 40 s/div dh 10v/div dl 10v/div v dd 10v/div input 5v/div typical operating characteristics (continued) (typical values are at v dd = v bst = +12v and t a = +25?, unless otherwise specified.)
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers 8 _______________________________________________________________________________________ figure 1. timing characteristics for noninverting and inverting logic inputs v ih v il 90% 10% t f in_h dh t d_on3 t d_off3 v ih v il 90% 10% v ih v il t r t r t f in_l (max15012a/c max15013a/c) in_l (max15012b/d max15013b/d) dl t d_on1 t d_on2 t d_off2 t d_off1 t match = (t d_on3 - t d_on1 ) or (t d_off3 - t d_off1 ) for "a/c" version t match = (t d_on3 - t d_on2 ) or (t d_off3 - t d_off2 ) for "b/d" version pin name function 1v dd power input. bypass v dd to gnd with a parallel combination of 0.1? and 1? ceramic capacitors. 2 bst boost flying capacitor connection. connect a 0.1? ceramic capacitor between bst and hs for the high-side mosfet driver supply. 3 dh high-side-gate driver output. driver output for the high-side mosfet gate. 4 hs source connection for high-side mosfet. also serves as a return terminal for the high-side driver. 5 in_h high-side noninverting logic input 6 in_l low-side noninverting logic input (max15012a/c and max15013a/c). low-side inverting logic input (max15012b/d and max15013b/d). 7 gnd ground. use gnd as a return path to the dl driver output and in_h/in_l inputs. 8 dl low-side-gate driver output. drives low-side mosfet gate. ?p exposed pad. internally connected to gnd. externally connect the exposed pad to a large ground plane to aid in heat dissipation (max15012c/d and max15013c/d only). pin description
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers _______________________________________________________________________________________ 9 detailed description the max15012/max15013 are 175v/2a high-speed, half-bridge mosfet drivers that operate from a supply voltage of +8v to +12.6v. the drivers are intended to drive a high-side switch without any isolation device like an optocoupler or drive transformer. the high-side driver is controlled by a ttl/cmos logic signal refer- enced to ground. the 2a source and sink drive capa- bility is achieved by using low r ds_on , p- and n-channel driver output stages. the bicmos process allows extremely fast rise/fall times and low propaga- tion delays. the typical propagation delay from the logic-input signal to the driver output is 35ns with a matched propagation delay of 2ns typical. matching these propagation delays is as important as the absolute value of the delay itself. the high 175v input voltage range allows plenty of margin above the 100v transient specification per telecom standards. the maximum operating supply voltage (v dd ) must be reduced linearly from 12.6v to 10.5v when the maxi- mum voltage (v hs_max ) increases from 125v to 175v. see the typical operating characteristics . undervoltage lockout both the high- and low-side drivers feature undervolt- age lockout (uvlo). the low-side driver? uvlo low threshold is referenced to gnd and pulls both driver outputs low when v dd falls below 6.8v. the high-side driver has its own uvlo threshold (uvlo high ), refer- enced to hs, and pulls dh low when bst falls below 6.4v with respect to hs. during turn-on, once v dd rises above its uvlo thresh- old, dl starts switching and follows the in_l logic input. at this time, the bootstrap capacitor is not charged and the bst-to-hs voltage is below uvlo bst . for synchro- nous buck and half-bridge converter topologies, the bootstrap capacitor can charge up in one cycle and nor- mal operation begins in a few microseconds after the bst-to-hs voltage exceeds uvlo bst . in the two-switch forward topology, the bst capacitor takes some time (a few hundred microseconds) to charge and increase its voltage above uvlo bst . the typical hysteresis for both uvlo thresholds is 0.5v. the bootstrap capacitor value should be selected care- fully to avoid unintentional oscillations during turn-on and turn-off at the dh output. choose the capacitor value about 20 times higher than the total gate capaci- tance of the mosfet. use a low-esr-type x7r dielec- tric ceramic capacitor at bst (typically a 0.1? ceramic capacitor is adequate) and a parallel combination of 1? and 0.1? ceramic capacitors from v dd to gnd. the high-side mosfet? continuous on-time is limited due to the charge loss from the high-side driver? qui- escent current. the maximum on-time is dependent on the size of c bst , i bst (40? max), and uvlo bst . output driver the max15012/max15013 have low 2.5 r ds_on p- channel and n-channel devices (totem pole) in the out- put stage. this allows for a fast turn-on and turn-off of the high gate-charge switching mosfets. the peak source and sink current is typically 2a. propagation delays from the logic inputs to the driver outputs are matched to within 8ns. the internal p- and n-channel mosfets have a 1ns break-before-make logic to avoid any cross con- duction between them. this internal break-before-make logic eliminates shoot-through currents reducing the operating supply current as well as the spikes at v dd . see the minimum input pulse width section to under- stand the effects of propagation delays on dh and dl. the dl voltage is approximately equal to v dd , the dh- to-hs voltage is approximately equal to v dd minus a diode drop, when they are in a high state and to zero when in a low state. the driver r ds_on is lower at higher v dd . lower r ds_on means higher source and sink cur- rents and faster switching speeds. internal bootstrap diode an internal diode connects from v dd to bst and is used in conjunction with a bootstrap capacitor externally con- nected between bst and hs. the diode charges the capacitor from v dd when the dl low-side switch is on and isolates v dd when hs is pulled high as the high- side driver turns on (see the typical operating circuit ). the internal bootstrap diode has a typical forward volt- age drop of 0.9v and has a 10ns typical turn-off/turn-on time. for lower voltage drops from v dd to bst, connect an external schottky diode between v dd and bst. driver logic inputs (in_h, in_l) the max15012a/b/c/d are cmos (v dd / 2) logic-input drivers while the max15013a/b/c/d have ttl-compati- ble logic inputs. the logic-input signals are independent of v dd . for example, the ic can be powered by a 10v supply while the logic inputs are provided from a 12v cmos logic. also, the logic inputs are protected against voltage spikes up to 14v, regardless of the v dd voltage. the ttl and cmos logic inputs have 250mv and 1.6v hysteresis, respectively, to avoid double pulsing during transition. the logic inputs are high-impedance pins and should not be left floating. the low 2.5pf input capaci- tance reduces loading and increases switching speed. the noninverting inputs are pulled down to gnd and the inverting inputs are pulled up to v dd internally using a 1m resistor. the pwm output from the controller must assume a proper state while powering up the device. with the logic inputs floating, the dh and dl outputs pull low as v dd rises up above the uvlo threshold.
max15012/max15013 minimum input pulse width the max15012/max15013 use a single-shot level-shifter architecture to achieve low propagation delay. typical level shifter architecture causes a minimum (high or low) pulse width (t dmin ) at the output that may be higher than the logic-input pulse width. for the max15012/ max15013 devices, the dh minimum high pulse-width (t dmin-dh-h ) is lower than the dl minimum low pulse width (t dmin-dl-l ) to avoid any shoot-through in the absence of external bbm delay during the narrow pulse at low duty cycle. see figure 2. at high duty cycle (close to 100%), the dh minimum low pulse width (t dmin-dh-l ) must be higher than the dl min- imum low pulse width (t dmin-dl-l ) to avoid the overlap and shoot-through. see figure 3. in case of the max15012/max15013, there is a possibility of about 40ns overlap if an external bbm delay is not provided. it is recommended to add external delay in the inh path so that the minimum low pulse width seen at inh is always longer than t pw-min . see the electrical characteristics table for the typical values of t pw-min . 175v/2a, high-speed, half-bridge mosfet drivers 10 ______________________________________________________________________________________ figure 2. minimum pulse-width behavior for narrow duty-cycle input (on-time < t pw-min ) pwmin dh dl t dmin-dh-h t dmin-dl-l inh inl dh hs n dl n v in v out v dd max15012b/ max15012d/ max15013b/ max15013d pwmin in-built dead time
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers ______________________________________________________________________________________ 11 figure 3. minimum pulse-width behavior for high duty-cycle input (off-time < t pw-min ) pwmin dh dl inh inl dh hs n dl n v in v out v dd external bbm delay max15012b/ max15012d/ max15013b/ max15013d pwmin inh inl dh hs n dl n v in v out v dd external bbm delay max15012a/c max15013a/c pwmin t dmin-dh-l t dmin-dl-h external bbm delay potential overlap time
max15012/max15013 applications information supply bypassing and grounding pay extra attention to bypassing and grounding the max15012/max15013. peak supply and output cur- rents may exceed 4a when both drivers are driving large external capacitive loads in-phase. supply drops and ground shifts create forms of negative feedback for inverters and may degrade the delay and transition times. ground shifts due to insufficient device ground- ing may also disturb other circuits sharing the same ac ground return path. any series inductance in the v dd , dh, dl, and/or gnd paths can cause oscillations due to the very high di/dt when switching the max15012/ max15013 with any capacitive load. place one or more 0.1? ceramic capacitors in parallel as close to the device as possible to bypass v dd to gnd. use a ground plane to minimize ground return resistance and series inductance. place the external mosfet as close as possible to the max15012/max15013 to further min- imize board inductance and ac path resistance. power dissipation power dissipation in the max15012/max15013 is pri- marily due to power loss in the internal boost diode and the nmos and pmos fets. for capacitive loads, the total power dissipation for the device is: where c l is the combined capacitive load at dh and dl. v dd is the supply voltage and f sw is the switching frequency of the converter. p d includes the power dis- sipated in the internal bootstrap diode. the internal power dissipation reduces by p diode , if an external bootstrap schottky diode is used. the power dissipa- tion in the internal boost diode (when driving a capaci- tive load) is the charge through the diode per switching period multiplied by the maximum diode forward volt- age drop (v f = 1v). the total power dissipation when using the internal boost diode is p d and, when using an external schottky diode, is p d - p diode . the total power dissi- pated in the device must be kept below the maximum of 0.471w for the 8-pin so package at t a = +70? ambient. layout information the max15012/max15013 drivers source and sink large currents to create very fast rise and fall edges at the gates of the switching mosfets. the high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. use the following pc board layout guidelines when designing with the max15012/max15013: it is important that the v dd voltage (with respect to ground) or bst voltage (with respect to hs) does not exceed 13.2v. voltage spikes higher than 13.2v from v dd to gnd or bst to hs can damage the device. place one or more low esl 0.1? decou- pling ceramic capacitors from v dd to gnd, and from bst to hs as close as possible to the part. the ceramic decoupling capacitors should be at least 20 times the gate capacitance being driven. there are two ac current loops formed between the device and the gate of the mosfet being driven. the mosfet looks like a large capacitance from gate to source when the gate is being pulled low. the active current loop is from the mosfet driver output (dl or dh) to the mosfet gate, to the mosfet source, and to the return terminal of the mosfet dri- ver (either gnd or hs). when the gate of the mosfet is being pulled high, the active current loop is from the mosfet driver output, (dl or dh), to the mosfet gate, to the mosfet source, to the return terminal of the drivers decoupling capacitor, to the positive terminal of the decoupling capacitor, and to the supply connection of the mosfet driver. the decoupling capacitor is either the flying capacitor connected between bst and hs or the decoupling capacitor for v dd . care must be taken to minimize the physical length and the impedance of these ac cur- rent paths. pcv fv diode dh dd sw f ? () ? 1 pcv f i i v d l dd sw ddo bsto dd = ? ? ? ? ++ () 2 175v/2a, high-speed, half-bridge mosfet drivers 12 ______________________________________________________________________________________
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers ______________________________________________________________________________________ 13 typical application circuits figure 4. max15012a/max15013a half-bridge conversion max15012a/c max15013a/c v out n n v dd = 8v to 12.6v v in = 0 to 175v* v dd bst in_h in_l gnd dl dh hs pwm controller pin compatible with the hip2100/hip2101 *derate v dd if v in increases above 125v. see note 3 in the electrical characteristics . figure 5. two-switch forward conversion max15012a/c max15013a/c n n v dd = 8v to 12.6v v in = 0 to 175v* v out v dd bst in_h in_l gnd dl dh hs pwm c bst *derate v dd if v in increases above 125v. see note 3 in the electrical characteristics .
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers 14 ______________________________________________________________________________________ max15012a/c gnd v dd in_h dh dl hs bst in_l 2 3 4 5 8 7 6 1 v dd /2 cmos so max15012b/d gnd v dd in_h dh dl hs bst in_l 2 3 4 5 8 7 6 1 v dd /2 cmos so max15013b/d gnd v dd in_h dh dl hs bst in_l 2 3 4 5 8 7 6 1 ttl so max15013a/c gnd v dd in_h dh dl hs bst in_l 2 3 4 5 8 7 6 1 ttl so functional diagrams
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers ______________________________________________________________________________________ 15 max15012b/d max15013b/d n n v dd = 8v to 12.6v v in = 0 to 175v* v out v dd bst in_h in_l gnd dl dh hs c bst pwm *derate v dd if v in increases above 125v. see note 3 in the electrical characteristics . typical operating circuit chip information transistor count: 790 process: hv bicmos in_l in_h hs 1 2 8 7 dl + gnd bst dh v dd so top view 3 4 6 5 max15012a/b max15013a/b in_l in_h hs 1 2 8 7 dl + gnd bst dh v dd so-ep 3 4 6 5 max15012c/d max15013c/d pin configurations part temp range pin- package pkg code max15013 aasa+ -40? to +125? 8 so s8-5 max15013basa+ -40? to +125? 8 so s8-5 max15013casa+* -40? to +125? 8 so-ep** s8e+14 max15013dasa+* -40? to +125? 8 so-ep** s8e+14 ordering information (continued) + denotes lead-free package. * future product?ontact factory for availability. ** ep = exposed pad.
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers 16 ______________________________________________________________________________________ soicn .eps package outline, .150" soic 1 1 21-0041 b rev. document control no. approval proprietary information title: top view front view max 0.010 0.069 0.019 0.157 0.010 inches 0.150 0.007 e c dim 0.014 0.004 b a1 min 0.053 a 0.19 3.80 4.00 0.25 millimeters 0.10 0.35 1.35 min 0.49 0.25 max 1.75 0.050 0.016 l 0.40 1.27 0.394 0.386 d d min dim d inches max 9.80 10.00 millimeters min max 16 ac 0.337 0.344 ab 8.75 8.55 14 0.189 0.197 aa 5.00 4.80 8 n ms012 n side view h 0.244 0.228 5.80 6.20 e 0.050 bsc 1.27 bsc c h e e b a1 a d 0 -8 l 1 variations: package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers ______________________________________________________________________________________ 17 8l, soic exp. pad.eps c 1 1 21-0111 package outline 8l soic, .150" exposed pad package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max15012/max15013 175v/2a, high-speed, half-bridge mosfet drivers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. heaney revision history revision number revision date description pages changed 0 5/06 initial release 1 12/07 added exposed paddle versions of the max15012a/b and max15013a/b, added figures 2 and 3 and added so-ep package outline 1?, 8?1, 13?7

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